LAUSR

ABSTRACT Managing the speed and power trade-off is becoming increasingly challenging as the power supply voltage (Vdd) is scaled down in each era. Existing logic circuits that address the trade-off require more power. A new logic circuit made up of one PMOS and two NMOS is evaluated while coupled to a typical power delivery network (PDN). Simulated in a 0.09 µm CMOS, the present circuit not only reduces the supply current but also achieves a constant delay than the CSL, MCML and CS-CMOS while the Vdd switches from 0.7 to 1.1 V. Besides, the power consumption and delay sustain a shift of 0.14µW and 0.3ps, respectively, following a 1OC change in temperature. However, the power consumption reduces by 0.2µW for a Vdd drop of 1mV. But the effective supply voltage close to the circuit fluctuates as the PDN draws a sudden high current. This causes the delay to change and induces jitter in the output swing. The jitter introduced for a current ramp 0–40A in 10ns is 6.7ps. The usefulness of the present design is also observed by designing a latch, master-slave flip-flop (FF), frequency divider (FD) and ring oscillator (RO). Comparing the latch, FF, FD and RO built using the conventional, proposed designs and simulated in a 0.09-µm CMOS show the lowest power and delay.