LAUSR

scale integration (VLSI). Leakage power, defined as the unwanted current flow when a transistor is in the OFF state, significantly impacts the power consumption and performance of VLSI designs, particularly during standby modes. Existing methods to reduce leakage power in SRAM cells often fail to strike a balance between power efficiency, stability, and performance under varying operational conditions. This study proposes a hybrid PNN-PPN 10T SRAM configuration incorporating leakage control transistors (LCTs) to mitigate leakage. The innovative design combines elements of PNN and PPN architectures, strategically integrating additional PMOS and NMOS transistors to create high-impedance paths between Vdd and ground. Using the CADENCE Virtuoso tool for circuit design and the Spectre simulator for performance evaluation, the proposed hybrid SRAM cell demonstrates significant improvements in key performance metrics. Results show a notable reduction in dynamic and leakage power consumption, enhanced speed with lower delay, and a reduced power-delay product (PDP) across varying voltage levels. Specifically, the inclusion of LCTs results in a substantial decrease in leakage power and delay, thereby contributing to overall energy efficiency and faster operation. Static noise margin (SNM) evaluation under read, write, and hold conditions further validates the robustness of the proposed design, ensuring reliable data retention and minimal leakage during standby modes. The study concludes that the proposed hybrid PNN-PPN 10T SRAM with LCTs offers a promising solution for low-power, high-performance memory applications, addressing the critical challenge of leakage power in advanced semiconductor technologies.