Micro/nanostructures with high aspect ratio in silicon wafer obtained by plasma etching are of great significance in device fabrication. In most cases, scallop nanostructure in deep silicon etching should be… Click to show full abstract
Micro/nanostructures with high aspect ratio in silicon wafer obtained by plasma etching are of great significance in device fabrication. In most cases, scallop nanostructure in deep silicon etching should be suppressed. However, scallop nanostructure could be applied in electronic device fabrication as characteristic information, which indicates the balance between deposition and etching. In this work, the applications of scallop nanostructure in etching process optimization and environmental protection are demonstrated. In addition, the minimum effect of the cycle time on the scallop size is reported for the first time. These results could bring new thoughts to the electronic devices related fields, such as micro-electro-mechanical systems (MEMS), silicon capacitors and advanced packaging.
               
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