LAUSR

A novel ultralow loss 4H-SiC double trenches MOSFET is presented and its mechanism is investigated by simulation. The device features two integrated heterojunction diodes (HJD) consisting of a P-type polycrystalline Silicon (P-ploy Si) and SiC, a trench split gate (SG) and P+ region (PR) beneath the source trench. Both the SG and PR reduce the coupling effect between gate and drain, and transform part of gate-drain capacitance (CGD) into gate-source capacitance (CGS) and drain-source capacitance (CDS). Compared with the conventional trench MOSFET (Con-TMOS) and the HJD trench MOSFET (HJD-TMOS), the proposed double trenches MOSFET with integrated HJDs and SG (HJD-SG-DTMOS) decreases the CGD by 83% and 89%, respectively. Moreover, the integrated HJDs take the place of the parasitic body diode as a freewheel diode, and thus reduce the reverse turn-on voltage. As a result, not only the reverse turn-on voltage of the proposed device is decreased by 69% and 33%, but also the switching loss is reduced by 64% and 49%, compared with those of Con-TMOS and HJD-TMOS, respectively.