LAUSR

In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while the write margin is 180 mV. Monte Carlo analysis for 6σ global variations and temperature variation analysis for temperatures in the range −10 °C to 80 °C validate its performance. The cell is compared with other single-ended 5T, 6T, 7T, 8T, 9T and 10T SRAM cells and is found to be superior in performance. As the leakage current is low, the I ON /I OFF ratio is high compared with the other cells. The power consumption of the bit cell is also found to be minimal for all modes of operation. The dynamic write analysis demonstrates that the proposed cell completes the write operation in a 10 ns pulse width. Moreover, the improvement in performance is obtained for an area as low as 0.539 µm2. The area of 5T, 6T, 7T-1, 7T-2, 7T-4, 7T-5, 8T, 9T and 10T cells is greater than the 7TP bit cell area by 22.17%, 51.8%, 35.8%, 13.9%, 30.4%, 6.78%, 56.6%, 63.3% and 75.5%, respectively.