Cadmium Sulfide (CdS) thin films were grown on crystal quartz as a nonconductive substrate, and Indium tin oxide (ITO) and Fluorine doped tin oxide (FTO) as transparent conducting oxide (TCO)… Click to show full abstract
Cadmium Sulfide (CdS) thin films were grown on crystal quartz as a nonconductive substrate, and Indium tin oxide (ITO) and Fluorine doped tin oxide (FTO) as transparent conducting oxide (TCO) films. The thin films with the thickness of 100 nm were fabricated at 150 °C under the pressure of 2 × 10−5 mbar using the thermal evaporation method. The x-ray diffraction (XRD) results showed that all grown CdS films had cubic crystal structures with the preferred orientation (111) and a crystallite size between 11.72 nm and 14.84 nm. Raman spectra also revealed an increase in peak intensity and shift toward single-crystal mode in the films grown on TCOs. The homogeneous and uniform surfaces of CdS films were shown in scanning electron microscopy (SEM) images. The optical parameters of the deposited CdS thin films such as absorption, transmission, refractive index, extinction coefficient, and real and imaginary parts of dielectric constant, were improved. The energy band gap of the films was decreased from 2.45 eV for the CdS/quartz film to 2.36 eV for the CdS/FTO one. The key electrical parameters of the deposited films on TCO, such as conductivity, mobility and carrier concentration, as calculated by the Hall effect measurement system, were enhanced too. High efficient heterojunction cadmium telluride (CdTe)-based solar cells with the experimentally grown CdS films were designed by SCAPS-1D simulator. The efficiency of the designed cells with CdS/quartz, CdS/ITO, and CdS/FTO layers was obtained to be 19.40%, 21.23%; and 21.16%, respectively. The impact of the CdTe absorber layer thickness and device temperature on the photovoltaic parameters of the simulated cells was then investigated. The optimized cell was obtained for an Au/CdTe/CdS/ITO structure with the efficiency of 22.80% by employing a 3 μm thickness of the CdTe layer at a device temperature of 300 K.
               
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