LAUSR

Purpose Maintaining a balanced neutral point, reducing power loss, execution time are important criteria for the controlling of neutral point clamped (NPC) inverter. However, it is tough to meet all the challenges and also supplying the load current within the harmonic limit. This paper aims to maintain load current quality within the Institute of Electrical and Electronics Engineers 519 standard and meet the above-mentioned challenges. Design/methodology/approach The output load current of a three-level simplified neutral point clamped (3 L-SNPC) inverter is controlled in this paper using model predictive control (MPC). The 3 L-SNPC inverters is considered because fewer semiconductor devices are used in this topology; this will enhance the reliability of the system. MPC is used as a controller because it can handle the direct current-link capacitors’ voltage balancing problem in a very intuitive way. The proposed 3 L-SNPC yields similar current total harmonic distortion (THD), transient and steady-state responses, voltage stress and over current protection capability as the conventional NPC inverter. To reduce the computational burden of the proposed SNPC system, two simplified MPC strategies are proposed, namely, single voltage vector prediction-based MPC and selective voltage vector prediction-based MPC. Findings The system shows a current THD of 2.33% at 8.96 kHz. The overall loss of the system is reduced significantly to be useful in medium power applications. The required execution times for the simplified MPC strategies are tested on the hardware dSPACE 1104 platform. It is found that the single voltage vector prediction-based MPC and the selective voltage vector prediction-based MPC are computationally efficient by 8.28% and 62.9%, respectively, in comparison with the conventional MPC-based conventional NPC system. Originality/value Multiple system constraints are considered throughout the paper and also compare the SNPC to the conventional NPC inverter. Proper current tracking, over-current protection, overall power loss reduction especially switching loss and maintaining capacitor voltages balance at a neutral point are achieved. The improvement of execution time has also been verified and calculated using hardware-in-loop of the dSPACE DS1104 platform.