This paper presents a modified Trellis Min–Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the… Click to show full abstract
This paper presents a modified Trellis Min–Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm2. When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of $3.25\times 10^{-6}$ at $E_{b}/N_{0} = 4.5$ dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled.
