LAUSR

Testing of real-time embedded systems (RTESs) under input timing constraints is a critical issue. Models which can specify timing constraints have respective merits and demerits and test suites which can cover more input possibilities and detect more faults under input timing constraints are worthy of study. In this paper, clocked computation tree logic which is used to specify input timing constraints is presented. Neighbor covering arrays and parallel input time correlation test suites are introduced to test RTESs under serial and parallel input timing constraints. Three algorithms are described in generating test suites, respectively, and corresponding random testing-based algorithms which are used as baselines for comparison are introduced. Benchmarks with different configurations are conducted to evaluate the algorithms’ performance. Three real-world RTESs are tested with the test suites described in this paper, respectively. The test results show that random testing may omit some neighbor input time point combinations as the randomness and increase test suite scales. This fact may lead to the omission of some faults and heavy costs. Therefore, the proposed test suites are more effective and efficient for testing RTESs under input timing constraints.