LAUSR

Broadband current-mode logic static divide-by-2 and divide-by-4 circuits fabricated in 65-nm CMOS are presented. The low-power frequency dividers are analyzed in a geometric way. The self-oscillation frequency and locking range of current-mode dividers are analyzed based on current vectors. A systematic design methodology is proposed to reduce power consumption and enhance the locking range. The divide-by-2 circuit operates from 8 to 40 GHz with 0 dBm input signal and consumes dc power of 4.6 mW with a 1.0 V supply. The divide-by-4 circuit operates from 12.4 to 38.4 GHz with 0 dBm input signal and consumes dc power of 7.5 mW with a 1.0 V supply. The core areas of divide-by-2/4 circuits are only $25\times 33\,\,\mu \text{m}^{2}$ and $47\times 28\,\,\mu \text{m}^{2}$ respectively.