The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the inactive rank within the redistribution layer (RDL). These reflections arrive at the active rank… Click to show full abstract
The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the inactive rank within the redistribution layer (RDL). These reflections arrive at the active rank within the unit-interval of the data-rate and distort not only the post-cursor but also the pre-cursor of the signal that the decision feedback equalizer (DFE) cannot remove. We introduce a differentiating receiver that restores data through edge information to eliminate the reflective distortions, including the pre-cursor, and a transition-detecting DFE to address remaining inter-symbol interference. A prototype receiver, fabricated in a 65 nm CMOS process, eliminates pre-cursor distortion with a reflection flight time of 50 ps and 70 ps, at 8 Gb/s and 6.4 Gb/s, resulting in a wide horizontal margin at a bit-error-rate of 10−12. The energy efficiency is 0.80 pJ/bit at 8 Gb/s.
               
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