LAUSR

With technology scaling, transistor sizing, as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells, used for aerospace applications, more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upsetrecoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells, RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs injected at all the sensitive nodes and SEMNUs that have occurred at its internal node-pair. In addition, EDP12T also exhibits better write performance than most of the comparison cells. Among all the cells for comparison, EDP12T dissipates the lowest hold power, except RHM12T. In addition to these, it consumes the least energy during write mode and also consumes lower energy than most of the comparison cells during read mode. It also exhibits 1.08×/ 1.17×/ 1.37×/ 1.56×/ 2.32× higher read stability than S8P4N16T/ RHPD12T/ QUCCE12T/ QUATRO12T/ LWS14T. All these aforementioned improvements are obtained by the proposed cell while consuming 1.03×/ 1.06×/ 1.07×/ 1.08×/ 1.14×/ 1.43× lower area than SAR14T/ RHD12T/ S8P4N16T/ RSP14T/ LWS14T/ RHPD12T. However, these advantages come with a slight penalty in read delay.