LAUSR

This paper provides an overview of blockchain technology’s security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip’s memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R= $42.3\Omega $ and R=42.3K $\Omega$ ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes $11.65~\mu \text{W}$ of power and has 33 transistors which are lowest from other architectures.