LAUSR

This paper presents a review of two-dimensional (2D) and three-dimensional (3D) electrical tomography (ET) hardware accelerators for real-time applications. While many recent review papers have discussed various algorithms for image reconstruction or acquisition systems, none of them has considered state-of-the-art hardware implementations of the associated image reconstruction algorithms to achieve real-time performance, especially for 3D ET where the computation requirement is excessively high. A 3D ET is useful in various applications such as robotics, autonomous vehicles, and process control, but it is computationally very expensive with respect to its 2D counterpart. Most implementations are based on single or multi-core CPUs and, to a lesser extent, on either graphics processing units (GPUs) or field programmable gate arrays (FPGAs). However, there is a clear gap between the currently available processors, whose computation power exceeds hundreds of teraflops per second (TOPS) at a reasonable low power consumption, and the ones recently used in ET systems. This gives great potential for next-generation ET systems to achieve real-time 2D and 3D ET reconstruction within a small form factor. The paper summarizes the most recent ET hardware systems with respect to their performance in terms of quality and processing frame rate, reconstruction methods, along with optimization and future directions.