LAUSR

Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner type DCC requires a large area and make the DCC unsuitable for applications that operate in a wide-range frequency. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line, while maintaining the performance of conventional DCC. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm2 and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz.