LAUSR

To meet the ever-increasing demands for small-lightweight consumer chargers, solutions to achieve higher switching frequencies are required. In this article, we show that it is essential to implement a synchronous rectifier for furthering advancements in power density. The shortcomings of diodes are illustrated, and their main disadvantage being their large power losses ranging from 600 to 2500 mW. We propose a synchronous rectifier based on a phase-locked loop (PLL). An application-specific integrated circuit containing a PLL designed for a synchronous rectifier was taped out in a 0.18- $\mu \text{m}$ CMOS process. The PLL has an area of 0.05 mm², and the total area containing two level shifters and gate drivers is 0.21 mm². Two main issues with the PLL-based synchronous rectifier are identified: the locking time and the rms jitter. The designed PLL achieves a sufficient phase noise performance of 8-ns rms jitter, which, from simulations, has been shown to have a minimal impact on the efficiency. The locking time of the PLL is measured to be 8 $\mu \text{s}$ . The resulting synchronous rectifier prototype showed a possible efficiency improvement of up to 1.8%, removing 1/8 of the total power loss, compared to a purely passive rectifier.