LAUSR

This article reports the demonstration of a low-voltage (<600V) monolithically integrated 4H-silicon carbide (SiC) MOSFET and JBS diode (JBSFET). A single-metal and thermal treatment process were implemented to form ohmic contacts on the n+ and p+ source regions while forming the Schottky contact on the N− SiC epitaxial layer. Different layout methodologies are discussed for fabricating an energy-efficient low-voltage JBSFET by intermittently placing the JBS diode portion in the orthogonal direction to minimize the device area, hence improving the specific ON-resistance and reducing the overall chip size by 46%. A junction termination extension (JTE)-based edge termination structure (the Hybrid-JTE) was implemented to achieve a high breakdown voltage with a very low leakage current. In addition, it was investigated that the forward characteristic of the JBSFET can be further improved by adopting Ti-based metal as the Schottky contact for the JBS diode. Device design, layout approach, fabrication, electrical characterization, and future prospects of the 4H-SiC JBSFETs are discussed in this article.