LAUSR

This is the first work that employs the body biasing feature, available in fully depleted silicon on insulator (FDSOI) technology nodes, to build CMOS-compatible compact majority (MAJ) and minority (MIN) logic gates. Compared to their CMOS counterpart, our novel MAJ/MIN gates exhibit considerably fewer transistors, $\boldsymbol {2.3} \times $ and $\boldsymbol {2} \times $ , respectively. The use of MAJ/MIN gates for logic synthesis has been widely investigated in the literature since any function can be realized using only these two gates. Nevertheless, the use of MAJ/MIN gates to synthesize circuits remained very limited because such gates are area hungry when implemented using conventional standard cells. Therefore, state-of-the-art research in the last decade has extensively focused on exploring beyond-CMOS technologies to build alternative MAJ/MIN gates. However, such emerging technologies are still immature and suffering considerably from variability. On the other hand, our novel FDSOI-based MAJ/MIN gates are based on mature CMOS commercial technologies. Our analysis of the proposed gates has been conducted using accurate SPICE simulations with an industry-compact transistor model, BSIM-IMG, calibrated for an industrial 14nm FDSOI technology. Using our developed MAJ/ MIN synthesis and error injection framework called MAJinBoo, we demonstrate that MAJ/MIN-based circuits exhibit an outstanding resiliency against errors due to the inherent voting-based computing. This encourages the employment of our MAJ/MIN gates in safety-critical applications where reliability is a prime concern. Our MAJinBoo framework is available at https://github.com/Brunno815/MAJinBoo.