LAUSR

A 0.065-mm2 single-channel calibration-free 12-b analog-to-digital converter (ADC) sampling at 600 MS/s in 28-nm ultrathin body bias fully depleted silicon on insulator (FD-SOI) is presented. The selected hybrid architecture, incorporating pipelined and asynchronous successive approximation register ADC, demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability of FD-SOI. Using an FBB voltage range of 0–1.8 V has enabled an signal-to-noise plus distortion ratio (SNDR) improvement of more than 9 dB. An integrated body bias generator ensures the required voltages for FBB. This paper demonstrates 61.5-dB and 60.7-dB SNDR at low and Nyquist input frequency, respectively, at 600-MS/s sampling frequency. The Walden FoM of 37.2 fJ/conv-step and Schreier FoM of 162.5 dB at 600 MS/s are achieved in Nyquist conditions. Speed robustness of the architecture has been demonstrated by achieving 57-dB SNDR at 800MS/s, >50-dB SNDR up to 950 MS/s, and 58.5-dB SNDR till 500-MHz input frequency at 600 MS/s.