LAUSR

This article presents a fractional-N digital multiplying delay-locked loop (MDLL) that employs a digital-to-time converter (DTC) to control the reference injection for the fractional-N operation. The presented MDLL features a background two-point DTC calibration that simultaneously corrects the DTC gain and offset errors to achieve a low-jitter and low-spur architecture. The DTC errors are sensed using an embedded time-to-digital converter (TDC) and extracted in the digital domain for reduced implementation overhead. A new TDC dithering and dither noise cancellation technique is used to improve the estimation accuracy of the DTC errors at the presence of TDC quantization error and differential nonlinearity (DNL). In addition, the adaptive dither noise cancellation scheme uses a comb filter to decouple the dither noise and DTC error estimations, allowing the two schemes to operate simultaneously. The proof-of-concept MDLL prototype fabricated in 65-nm CMOS achieves -60-dBc fractional spur and 1.67-ps rms jitter at around 20-MHz offset. With the proposed calibration scheme, a >25-dB spur reduction in reference and fractional spurs is demonstrated.