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Demand for dynamic random access memory (DRAM) bandwidth has outpaced DRAM transistor performance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6… Click to show full abstract
Demand for dynamic random access memory (DRAM) bandwidth has outpaced DRAM transistor performance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6 with costly high bandwidth memory (HBM), this article presents a solution that simultaneously increases pin and energy efficiency through the integration of four-level pulse amplitude modulation (PAM-4) into the single-ended memory interface. Building upon the existing GDDR6 architecture, evolutionary modifications to input, output, clocking, and data path, along with the component package design, enable a per-pin data rate of more than 22 Gb/s.
Journal Title: IEEE Journal of Solid-State Circuits
Year Published: 2022
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