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This article presents the design, implementation methodology, and validation of a multi-bit flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single-event transients (SETs) caused by radiation strikes.… Click to show full abstract
This article presents the design, implementation methodology, and validation of a multi-bit flip-flop (FF) system that provides tolerance against single-event upsets (SEUs) and single-event transients (SETs) caused by radiation strikes. The proposed solution also has embedded timing pre-error sensing capability, which enables closed-loop integration of digital systems to work at optimal operating point (OPP) without any fail. It allows efficient real-time dynamic voltage frequency scaling (DVFS) implementation in the digital system. It helps detect aging-related and total ionizing dose (TID)-induced timing degradation in digital circuits. It can be implemented with any standard digital cell library (non-rad-hard), thereby providing a cost-effective solution for rad-hard applications. The design is implemented in ST BCD 90-nm technology in multiple configurations of bit sizes. A digital system based on ARM cortex M4 microprocessor has also been implemented with the proposed FF and put on silicon for testing to validate various capabilities of the proposed design. The results are presented based on simulations, electrical characterization, and radiation tests.