This article presents an all-digital hardware accelerator for solving partial differential equations using the finite difference method (FDM) with dynamically reconfigurable computing bit precision. The proposed accelerator consists of 21… Click to show full abstract
This article presents an all-digital hardware accelerator for solving partial differential equations using the finite difference method (FDM) with dynamically reconfigurable computing bit precision. The proposed accelerator consists of 21 $\times $ 21 bit-serial processing elements (PEs) to compute 2-D grid solutions with massive parallelism. The 21 $\times $ 21 bit-serial PEs are connected in a lattice structure, and a PE communicates with four neighboring PEs to update the grid solutions. A PE comprises four key building blocks: a bit-serial adder, a shift register, 4:1 multiplexers, and an accumulator. The proposed hardware accelerator minimizes data movement based on its array architecture that directly maps a 2-D grid of the FDM. Besides, the proposed residue-based bit-serial computation method lowers energy consumption and latency. The checkerboard update method further improves the performance by updating the solutions in two cycles regardless of the grid size. A test chip is fabricated using 65 nm, and a 21 $\times $ 21 PE array occupies 0.462 mm2. The measured energy consumption is 1.59 nJ per iteration at 16 bit, 1 V, and 25.6 MHz.
