Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter… Click to show full abstract
Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In this article, we show an example of a time-interleaved analog demultiplexer (ADeMUX) with four track-and-hold (T/H) circuits based on switched emitter followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar-CMOS (BiCMOS) technology for parallel operation of four CMOS ADCs. The 50% duty cycle of the clock signal facilitates its generation and can save power consumption in the clock path or enable higher sampling rates compared with the 25% duty-cycle clock of other ADeMUX architectures. We show that using switched preamplifiers in front of the SEFs can double the bandwidth of each T/H lane. Experimental verification shows up to 57-GHz input bandwidth while requiring only 16-GHz input bandwidth for each of the ADCs that can be connected to the four 32-GS/s output channels. The circuit achieves 3–6-bit accuracy and is suitable for 100-GBd signaling and beyond with pulse amplitude modulation. To demonstrate the capability of higher sampling rates, measurement results at 4 $\times $ 50 GS/s = 200 GS/s are provided as well although significant advancement of the measurement environment is needed for a complete evaluation.
               
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