LAUSR

To design a low-oversampled high-resolution noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be addressed. One is to implement high-order optimized NS with simple and low-power hardware that maximally preserves a SAR’s efficient nature, and the other is to alleviate the sampling noise and input driving burden. This article presents a fourth-order NS-SAR ADC that synergistically addresses both challenges. It proposes an innovative error feedback-cascaded resonator feed-forward (EF-CRFF) structure and a noise-mitigated buffer-in-loop (BIL) technique. The former balances the robustness and energy efficiency by combining the merits of EF and CRFF structures, while the latter ensures the ADC to be low noise and easy-to-drive simultaneously. Prototyped in 65-nm CMOS technology, this work achieves 84.1-dB signal-to-noise-distortion ratio (SNDR) with 500-kHz bandwidth (BW) under a small OSR of 5. The prototype consumes 133.8- $\mu \text{W}$ power under 1.2-V supply (including the power of in-loop buffer under 2-V supply), leading to a 180-dB Schreier figure of merit (FoM).