LAUSR

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5–100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 $\mu \text{s}$ .