LAUSR

Scaling down DRAM technology degrades cell reliability due to increased coupling between adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency of certain cells (hot cells) may cause data loss in neighboring cells in adjacent rows due to crosstalk, which is known as row hammering. In this work, the goal is to mitigate row hammering in DRAM cells through a Counter-Based Tree (CBT) approach. This approach uses a tree of counters to detect hot rows and then refreshes neighboring cells. In contrast to existing deterministic solutions, CBT utilizes fewer counters that makes it practically feasible to be implemented on-chip. Compared to existing probabilistic approaches, CBT more precisely refreshes rows vulnerable to row hammering based on their access frequency. Experimental results on workloads from three benchmark suites show that CBT can reduce the refresh energy by more than 60 percent and nearly 70 percent in comparison to leading probabilistic and deterministic approaches, respectively. Furthermore, hardware evaluation shows that CBT can be easily implemented on-chip with only a nominal overhead.