LAUSR

In current generation digital phase-locked loop (DPLL) architectures, techniques like gear-shift mechanism and switched phase-detection are employed to achieve better lock time and jitter performance. This letter presents a framework for detailed analysis of the stability and settling behaviour of switched DPLL architectures using Lyapunov theory. The loop-parameters verified based on these stability conditions ensure that chattering does not occur during switching between different subsystems. A 5 GHz DPLL designed with these loop parameters and an error-tracking finite state machine (ET-FSM) is presented in this letter. The state machine with a bang-bang phase detector (BBPD) aids in faster locking by tracking the settling behaviour of the loop in the previous clock cycles, and accordingly deciding the loop parameters. The DPLL with lock in around 100 clock cycles for 100 MHz reference clock, obtained using MATLAB and schematic simulations, verifies the efficacy of the state machine.