LAUSR

In this letter, we have studied the impact on lateral nanowire transistor's (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NW's gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nm-diameter-based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, overall device speed is lagging behind the 7-nm diameter device.