LAUSR

Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access memory (RRAM) array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R array by cascading NAND gates. This letter presents a feasible approach to in-memory computing for large-scale circuits.