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The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is… Click to show full abstract
The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside. An electro-thermal-mechanical simulation is performed to reproduce the failure transition, and it reveals that the crack forms at an early stage. This new failure mechanism further enlightens on the vulnerability of the vertical power MOSFET structure in extremely high-temperature operation.
Journal Title: IEEE Electron Device Letters
Year Published: 2020
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