LAUSR

We develop a novel scheme to realize data search in NAND flash memories, which is important for a wide variety of applications in data centers. In our design, the pair unit consists of double neighbor cells in the NAND string, one “data cell” and one “complementary cell”. The NAND string will be at the “Pass” state only when the searching data are completely matched with the stored data. Parameters that affect data search performance are analyzed systematically. Based on simulations in vertically stacked 3D NAND structures, it is shown that the bit-line current ratio of the fully matched case to the worst case of one mismatched data is more than ~104 in both MLC (multi-level cell) and TLC (triple-level cell) modes, and ~102 can still be obtained in QLC (quad-level cell) mode after read voltage optimizations. These results indicate that the proposed scheme is effective for data search in multi-level NAND flash memories and also friendly for peripheral circuits design.