LAUSR

A $V$ -band CMOS frequency tripler with efficient input–output, and interstage matching networks is proposed to improve the output power and conversion efficiency. The interstage matching network, located between a tripler-core and a buffer amplifier, simultaneously performs the impedance matching of a desired third harmonic signal and the filtering of unwanted fundamental and even harmonic signals, without an additional power loss in a small area. Wideband operation and differential signal balance characteristics are achieved at the input and output by using a transformer-based balun with a compensation capacitor. The proposed tripler was implemented in a size of 0.476 mm2 using the TSMC 65-nm CMOS technology. Measurement results show a saturated output power of 6.4 dBm with a harmonic rejection of 37 dBc for an input power of 10 dBm at 59.4 GHz. The maximum conversion efficiency is 3.92% with an input power of 6.5 dBm at 59.4 GHz.