LAUSR

& MODERN MICROPROCESSOR CHIPS have multiple processing engines (or cores) that are architected to solve a variety of problems in individual and cooperative execution modes. In the current regimeof commercial designs,we already see double-digit core counts; and if one considers the degree of hardware multithreading supported in each core, the number of hardware threads that can be supported in concurrent execution add up tomany dozens or scores. For example, IBM’s prior generation POWER8 processor chip already supported up to 96 hardware threads via its 12 cores, each of which can execute in up to an eight-way simultaneously multithreaded mode. As explained in recent ISSCC technology trend data, while the core count growth has been steady, the clock frequency has saturated around the 4GHz mark—mainly limited by power density (or temperature) constraints. Effective parallelization of application codes, supported by many-core/ many-thread hardware engines, is the established trend in current computing. Since 96-thread POWER8 server chips have already been in the market for a few years, it is not unrealistic to expect around 50 cores and perhaps 200 hardware threads supported in a couple of generations. Of course, due to area pressures, one can expect to see leaner (simpler) cores with only modest single-thread performance growth. This technologyand marketdriven trend toward throughputoriented (scale-out) designs implies a major challenge in terms of chip-level power and/or thermal management—in a regime where balanced performance growth (single-thread versus throughput) at affordable power becomes a steeper challenge over time. And, at the full system (i.e., server, rack, or data center) level, the challenge can be even greater. At whatever scale one is interested inmanaging suchmetrics (i.e., power or temperature, or even related ones, like system reliability), Digital Object Identifier 10.1109/MM.2019.2921508