LAUSR

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15-V tolerant radiation-hardened MOSFET driver is designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5 V, allowing the selection of thin gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors help the driver to obtain a good resilience to TID hardness. In addition, this work optimizes the layout of high-voltage N-type laterally diffused metal oxide semiconductor transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths are designed and fabricated in a 0.35-$\mu \text{m}$ bipolar-CMOS-DMOS (BCD) process. The test results show that the TID hardening capability of these chips with zener references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver is tested under heavy ion irradiation with linear energy transfer exceeding 75 MeV$\cdot \mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$. The results show that this driver with a 6.6-$\mu \text{m}$ drift region length has no single-event latch-up, single-event gate rupture, or SEB sensitivity.