LAUSR

There has been a growing demand for energy efficient and high performance password recovery systems. As password generation and password validation are two integral components of any password recovery system, the former yet lags behind the latter in performance particularly for the case when the popular rule-based password generation method is applied to the heterogeneous CPU-FPGA system. In this paper, we thus present a high performance, energy efficient accelerator to speed up the rule functions in rule-based password generation. Dubbed RUPA, this proposed accelerator explores previously undiscovered computational features and memory access patterns for processing the rule functions. Specially, we show that the rule functions can be mapped to three distinct groups according to their character dependency graphs. Correspondingly, three kinds of datapath units, referred to as rule logic units, are created, and the rule functions from the same group will be processed in their shared rule logic unit. Compared with the state-of-the-art password recovery system built upon a CPU-GPU platform, the FPGA-based RUPA system achieves 5.3x speed improvement and is 33.1x more energy efficient. If RUPA is integrated into the popular password recovery tool John the Ripper (JtR), JtR's rule-based attack performance can soar by more than 48.7x.