LAUSR

As feature sizes in semiconductor technique scale down, traditional CMOS devices and interconnects are facing several challenges. Graphene nanribbon (GNR)-based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a set of nets in a single-layer GNR routing (SGNRR) plane, an efficient routing algorithm can be proposed to maximize the number of the routed nets with minimizing the bending delay in SGNRR. The routing process in our proposed algorithm can be divided into three sequential steps: 1) routability-driven net assignment; 2) iterative diffusion-based transformation for delay reduction; and 3) iterative rip-up-and-reroute (IRUR) for delay reduction. In routability-driven net assignment, based on the transformation of multiple-pin nets and the region extraction of two intersected nets in single-layer routing, some detored nets can be selected and the remaining nets can be first routed inside their available regions. Furthermore, the detored nets can be routed by using single-layer obstacle-aware routing. In iterative diffusion-based transformation for delay reduction, the available empty space in an initial routing result can be further used to transform 120° bends into 60° bends. In IRUR process for delay reduction, the routing order of two adjacent nets may be further exchanged to reduce the bending delay if empty space is available. Compared with the combination of the transformation of multiple-pin nets and Yan’s negotiated congestion-based algorithm in SGNRR, the experimental results show that our proposed algorithm can use less CPU time to decrease 11.1% of total bending delay with increasing 1.3% of total wirelength on the given nets with the same 100% routability for six tested examples on the average. Additionally, the experimental results show that our proposed algorithm can use less CPU time to increase 5.5% of routability on the given nets for six denser examples on the average.