LAUSR

In an IC used for safety-critical applications, the Fault and soft-error tolerance (or FET) is often desirable. In this work, we consider a graceful degradation scheme, as the second line of defense, for a FET delay-locked loop (DLL) we have recently developed. By doing so, a FET DLL will not operate blindly when its tolerance to faults or soft errors has been degraded. This is achieved by incorporating a novel low-cost excessive phase-error monitor. Any excessive phase error beyond a prelearned phase-error tolerance range will trigger an alarm of failure. This monitor can also be used to support an online test for deciding whether there is a faulty module in our TMR-based FET DLL at any given time. We have implemented the proposed scheme in a 90-nm CMOS process. The results show that the area of this excessive phase error monitor is as small as 60 $\mu \text{m}\,\,\times $ 60 $\mu \text{m}\,\,=$ 0.0036 mm², or only 4.12% of the entire FET DLL.