LAUSR

Electromigration (EM) is crucial for interconnect reliability. This article introduces the implementation and application of CacheEM which targets SRAM cache memory aging due to EM. CacheEM is based on a comprehensive framework including five parts: 1) microprocessor emulation; 2) memory cell array activity extraction; 3) computation of currents in segments of long complex interconnect structures; 4) evaluation of the time-dependent hydrostatic stress and the resistance shift of interconnects; and 5) characterization of the EM lifetime distribution of interconnects in the cache memory. The first two steps (top-down) are implemented with gem5 and cache simulation, respectively. These simulators export the number of read and write operations for each cell of a cache memory in a microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution in each interconnect segment as the third step (bottom-up). The currents due to read and write operations are stored in models which have been pretrained with a regression algorithm. These models provide accurate predictions of the corresponding currents under various parameter settings, such as temperature, supply voltage, and gate length. Afterward, the samples of time-dependent hydrostatic stress and the resistance shift in each interconnect segment are computed while incorporating the variations of the effective activation energy and critical stress. The EM lifetime distribution of the cache memory is extracted using predefined threshold values. The impact of configuration parameters on EM reliability and performance of the SRAM cache is analyzed by comparing EM lifetime distributions.