LAUSR

Due to the mismatch between the package scaling and the relentless silicon technology scaling, the limited power supply bumps have to bear more stresses on bump reliability. A too high through-bump (TB) current may induce increased thermal and mechanical issues, thereby damaging the integrity of the solder joint microstructure. Thus, it is critical to analyze the TB current under different test scenarios at sign-off to ensure bump integrity. Since the full chip power delivery verification (PDV) needs to solve a linear system with billions of nodes, it is then very time- and resource-consuming to repeatedly conduct such bump integrity check during ECO. In this article, we present a fast TB current estimation methodology for PDV, which can significantly reduce the computational complexity while maintaining accuracy. The experimental results demonstrate that the proposed methodology can achieve very high accuracy with a relative error of around 0.6% and a maximum error of around 1.5% across four different designs with 1–2 orders of magnitude speed-up.