LAUSR

This paper presents inherently accurate digital calibration of ADC non-linearity, which requires neither absolute accuracy of a signal for calibration nor any modification of ADC core, hence enabling the use of existing ADC IP cores. It only relies on constant attenuation ratio provided by a passive resistive attenuator and hence it is inherently accurate as exemplified by extensive simulations as well as comparison with conventional method. A prototype $0.35\mu \text{m}$ -CMOS cyclic ADC with the on-chip signal generator for calibration has achieved the noise-limited 71.2-dB SNDR after the calibration under the sampling rate of 300 kS/s with 1.0-mW power and 0.087-mm2 chip area. The proposed calibration can be applied to the pipelined and cyclic ADCs with finite-gain non-linear op-amps as well as the SAR ADC.