LAUSR

The benefits of the ordering technique to improve the static linearity performances of digital-to-analog converters are discussed. Different techniques of grouping or sequencing elements are studied for segmented, binary or unary DAC architectures. The statistic of ordered elements and their properties are reviewed and studied. Then, the optimal selection of elements for a binary or unary use is discussed. The paper also estimates the limit caused by gradient, a systematic offset, and a non detected interval in the comparator used for the sorting. Results show that the use of segmented architecture with 8~16 groups of elements sorted and optimally selected grants 2~3 bits more in the performance. The benefit can become 5 bits for 128 groups at the cost of more significant efforts for the ordering.