LAUSR

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of -45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.