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This paper presents signal-independent background calibration for timing errors in time-interleaved ADCs, using a random ramp-based calibration signal. A prototype 10-b 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With… Click to show full abstract
This paper presents signal-independent background calibration for timing errors in time-interleaved ADCs, using a random ramp-based calibration signal. A prototype 10-b 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the SNDR is 50.1 dB at Nyquist while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Freezing the calibration after convergence improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step.
Journal Title: IEEE Transactions on Circuits and Systems I: Regular Papers
Year Published: 2022
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