LAUSR

This brief presents a fully integrated cross-coupled voltage multiplier for boosting dc-to-dc converter applications. The proposed design applies a new structure of cross-coupled voltage doubler (CCVD) and a clock scheme that eliminates all of the reversion power loss and increases the power efficiency (PE). In addition, this design is scalable to multiple-stage voltage doubler (voltage multiplier) as the maximum gate-to-source/drain or drain-to-source voltage does not exceed the nominal power supply $V_\mathrm{dd}$. As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13-$\mu\text{m}$ IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.