In this brief, a hybrid-grained reconfigurable architecture (HReA) is introduced to process 13-Dwarfs. The proposed dynamically reconfigurable fabric consists of four $4\,\,{\times } \,\, 4$ multi-functional processing elements array, where… Click to show full abstract
In this brief, a hybrid-grained reconfigurable architecture (HReA) is introduced to process 13-Dwarfs. The proposed dynamically reconfigurable fabric consists of four $4\,\,{\times } \,\, 4$ multi-functional processing elements array, where a hybrid-grained structure is proposed to combine a 32-bit data path with a 1-bit data path to accommodate multiple computing granularities in 13-Dwarfs. Aiming at the flexibility of the 13-Dwarfs calculation, a directional broadcasting scheme for multi-bank memory, a cache partitioning mechanism, and cache prefetching methods are proposed to further improve HReA performance via alleviating data and configuration bandwidth bottlenecks. The HReA is implemented on a $4.83\,\, {\times } \,\, 4.93$ mm2 silicon with TSMC 65-nm LP1P8M CMOS technology and can efficiently perform 27 representative kernels from the 13-Dwarfs with 297 mW under 280-MHz working frequency.
