LAUSR

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7-MHz bandwidth and a Walden figure-of-merit of 341 fJ/conversion.