A 30 MHz–3.6 GHz wideband frequency synthesizer with a self-biased oscillator and quadrature-input quadrature-output (QIQO) dividers for software-defined radio applications is presented in this brief. The self-biased oscillator employs a… Click to show full abstract
A 30 MHz–3.6 GHz wideband frequency synthesizer with a self-biased oscillator and quadrature-input quadrature-output (QIQO) dividers for software-defined radio applications is presented in this brief. The self-biased oscillator employs a novel cross-coupled negative-Gm pair that performs an equivalent linearized negative resistance, mitigating the noise folding process. The QIQO dividers are utilized to divide the quadrature signals and incorporate with a quadrature single sideband mixer for post synthesizing. The synthesizer is implemented in TSMC 180-nm RF CMOS process and provides a phase noise performance of −125.4 dBc/Hz and −122.9 dBc/Hz at 1 MHz offset under 1.8- and 2.7-GHz carriers, respectively. The maximum power consumption is 135 mW and the die size, including pads and I/O is 2.9 mm $^{{2}}$ .
               
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