LAUSR.org creates dashboard-style pages of related content for over 1.5 million academic articles. Sign Up to like articles & get recommendations!

A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits

Photo from wikipedia

Logic locking, a popular countermeasure against IP piracy and counterfeiting, has been a target of several attacks, especially Boolean satisfiability attacks. The state-of-the-art solutions against SAT attack struggle to meet… Click to show full abstract

Logic locking, a popular countermeasure against IP piracy and counterfeiting, has been a target of several attacks, especially Boolean satisfiability attacks. The state-of-the-art solutions against SAT attack struggle to meet a fundamental criterion of logic locking, i.e., high output corruption for wrong keys. In this brief, we propose a new logic locking scheme, called Encrypt Flip-Flop, which mitigates SAT attack on sequential circuits by preventing unauthorized access to the scan data. Security analysis on Encrypt Flip-Flop demonstrates its ability to thwart other advanced attacks like path sensitization, logic cone-based, removal, bounded model checking, etc., on reasonably large circuits. Experimental results on ISCAS’89 and ITC’99 benchmarks show that our proposed method can produce reasonable output corruption for wrong keys.

Keywords: sequential circuits; guided design; logic locking; obfuscation guided; security; scan obfuscation

Journal Title: IEEE Transactions on Circuits and Systems II: Express Briefs
Year Published: 2020

Link to full text (if available)


Share on Social Media:                               Sign Up to like & get
recommendations!

Related content

More Information              News              Social Media              Video              Recommended



                Click one of the above tabs to view related content.