LAUSR

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and improves the loop stability at the same time. What’s more, the high voltage regulator used in the conventional wordline voltage generator is not necessary anymore. The proposed generator has been implemented in a 0.18 $\mu \text{m}$ triple-well CMOS process, and the effective chip area is 0.55 mm2. Under the equivalent load conditions of 3D NAND flash, the measurement results show that the maximum ripple voltage is 2.06 mV, and the ripple is independent from clock frequency and output voltage. Moreover, the peak efficiency is about 36% at 23 V output voltage.